Preparation of ramp-edge interface modified junctions for HTS SFQ circuits

We have studied the properties of ramp-edge interface modified Josephson junctions (IMJs) whose barriers are formed during the etching process and subsequent annealing process. We investigate the effect of process parameters on junction characteristics (I/sub c/, R/sub n/) and obtain an empirical equation concerning their relationship. We select accelerating voltage (V/sub acc/) and etching time (t/sub etch/) for the control of I/sub c/ of IMJs and set the target value of I/sub c/ at 4.2 K to 500 /spl mu/A in this study. This target value can be realized by V/sub acc/=500 V and t/sub etch/=20 min from our empirical equation. We prepare four different samples fabricated in the same conditions, and examine the reproducibility and controllability of I/sub c/. The obtained I/sub c/s are very close to the target value, and the run-to-run spread is confined to about 150 /spl mu/A. The reproducibility and controllability of I/sub c/ are improved compared to our previous data of junctions with artificial barriers.