Contents 1. Introduction
Conventional error correcting codes (ECCs) used in digital communications such as BCH or Reed-Solomon codes are known to be inadequate for on-chip DRAM applications. The encoding and decoding circuits of these codes employ a linear feedback shift register (LFSR), which, if used in a DRAM chip, will introduce very high access delay [1], [2], [3]. Owing to this constraint, Hamming or extended Hamming codes are usually used. At system level, 32 bit word, DRAM chips use a binary systematic (38, 32) code, known as extended Hamming code to correct a single error. In this paper, we present an alternative fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting code. The fast (41, 32, 3) code reduces significantly circuit complexity and power consumption, with only three extra parity-bit penalty. This new code is constructed by generalizing the basic idea given by fast, ultimate binary systematic (8, 4) single-error-correcting code. Fast, ultimate (8, 4, 3) is presented in section 2. In section 3, fast, minimal decoding complexity, system level, systematic (41, 32, 3) code is constructed [5]. Section 4, present the advantage of this new (41, 32, 3) code in term of circuit complexity, power dissipation and propagation delay.
