Voltage handling capability and termination techniques of silicon power semiconductor devices

Firstly, the author revisits the methodology used to calculate the avalanche breakdown voltage of power semiconductor devices. He shows that the classical formulations using Van Oversraeten ionisation coefficient can lead to an underestimation of about 45% regarding the voltage handling capability. Next a review is presented of the major termination techniques used today in microelectronics, mainly planar compatible. Their principle is shown and some general considerations about their drawbacks and advantages given. A comparison is given regarding some criteria such as their static and dynamic efficiency, the space used, the voltage range covered, the ease of design and the technological feasibility.