A new 800 V lateral MOSFET with dual conduction paths

A novel 800 V lateral MOSFET is presented. The key feature of this new device is a buried P-type layer that divides the N-type drift region into two parallel conduction paths. The dual conduction paths provide an on-state resistance reduction of 33% as compared with a state-of-the-art double RESURF MOSFET. Charge balance is maintained among the layers to ensure high blocking voltage capability. The manufacturing process is relatively simple and provides excellent control of the charge in each layer by using ion implantation steps rather than epitaxial layers. A new BiCMOS Power IC process, featuring this novel device, is used to manufacture cost-effective integrated power supply chips.