A CMOS R-2R ladder digital-to-analog converter and its characterization

A digital-to-analog (D/A) converter based on the R-2R ladder is first analyzed in terms of the power consumption, to point out that the current-mode is the lowest power dissipation counter-part of the voltage-mode. The integral nonlinearity (INL) analysis and the characterization methods of the current-mode D/A converter are then presented to identify the error sources. The methods are applied to an 8-bit D/A converter fabricated using 0.6 /spl mu/m CMOS process. Measured results compared with INL analysis indicate that the dominant error source of a prototype converter is the resistance of the metal interconnect between the ladder and the bonding pad, and INL of the ladder itself is 1.2 LSB.