Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

In this paper, a focused review is made of our previously reported (2002-2007) work on negative-bias temperature-instability (NBTI) measurement and analysis. Using suitable cross-reference to other published work, the impacts of stress condition, characterization technique, and gate-oxide process on measured NBTI parameters are reviewed. The large scatter of measured time, bias, and temperature dependencies of NBTI, which are observed in published literature, is carefully analyzed. A common framework for NBTI physical mechanism is suggested and discussed. Issues lacking proper understanding at present are also highlighted.

I. Introduction

Negative bias temperature instability (NBTI) of p-MOSFET parameters, i.e., threshold voltage , linear and saturation drain current, transconductance , etc., is an important reliability concern for modern ICs. Although first observed during 1970s [1], NBTI has resurfaced in the past ten years, both for mainstream digital and analog devices [2]–[9]. This is due to the introduction of surface channel p-MOSFETs for analog circuits and the scaling of gate oxides below 2 nm for digital circuits, without proportionate scaling of supply voltages. In particular, the incorporation of nitrogen in sub-2-nm gate oxides (to prevent boron penetration and reduce gate leakage) has presently made NBTI the most crucial reliability concern [10]–[27].