I. Introduction
A major challenge in today's chip design is to integrate analog and digital circuits in one chip. Thereby, parasitic structures arise, which might affect the functionality. One of these parasitic structures is the lateral parasitic bipolar transistor in junction-isolated Smart Power ICs [1]–[3]. The parasite is activated when negative voltages (down to 1.5 V) occur in power stages. This happens even during normal operation and causes the injection of minority carriers into the substrate, which leads to minority carrier collection by sensitive tubs in input/output (I/O) and analog cells, which, in turn, causes potential failures. These collected currents may cause latchup or change logic states. In the following, we focus on p-substrates. The effects are identical in an n-substrate, and the model equations can be easily transferred to n-substrates. Furthermore, we focus on lightly doped -substrates where the substrate currents may flow several hundred micrometers in contrast to -substrates with a thick p-epitaxial layer.