I. Introduction
In today's semiconductor industry, the debug of chips after the arrival of first silicon is increasingly important, both for shortening the time to market and for improving the yield and/or performance of products as they reach high-volume manufacturing. At the same time, debug is becoming increasingly complex and difficult. For instance, the original chip designers are often preoccupied with new designs as the former ones reach high-volume production, with a limited availability for debug- or yield-diagnostic work. This problem is exacerbated by the extensive reuse of intellectual property (IP) blocks, into which the designers often have limited visibility. In many cases, the layout, schematics, netlists, etc., may be unavailable. Furthermore, the design-process interactions are becoming an increasingly common source of bugs and yield loss in modern ICs. It is no longer possible to guard band against all worst case process variations in designs, and slight process skews can often cause a significant or total loss of yield. The time pressure is enormous, and yet risk tapeouts are also becoming prohibitively expensive. Thus, simple yet powerful tools are necessary for the rapid identification of yield-impacting design issues. Among such tools, optical probing is becoming increasingly useful.