Chip-level soft error estimation method

This paper gives a review of considerations necessary for the prediction of soft error rates (SERs) for microprocessor designs. It summarizes the physics and silicon process dependencies of soft error mechanisms and describes the determination of SERs for basic circuit types. It reviews the impact of logical and architectural filtering on SER calculations and focuses on the structural filtering of soft radiation events by nodal timing mechanisms.

I. Introduction

Soft ERRORS have been extensively studied in the decades since the discovery of their impact on memory cells and logic circuits [1], [2]. Early studies dealt with the physics of the phenomenon, examining and modeling the interaction of particles with very large scale integration (VLSI) structures. Later studies sought to determine the error rate of specific circuits and to define process trends. Much work was also dedicated to soft error prevention, focusing on process dependencies, circuit hardening, fault tolerance, redundancy, and error correction schemes. The IBM Research Journal Special Issue on Soft Errors (January, 1996) provides a compelling summary of the work done at IBM from the beginning of that company's work on soft errors in VLSI circuits [3]–[8].