I. Introduction
The incident alpha particles or other ionized particles (from the radioactive decay of packaging material itself or from the environment) introduce single-event transients (SETs) in CMOS digital circuits [1]. This problem is becoming severe for advanced technologies where smaller capacitances and smaller drive currents result in lower charge requirements for a SET. As a result, such SETs are fast becoming a major concern for integrated circuit (IC) and system designers. In this paper, circuit design techniques are presented that mitigate the effects of SET pulses by eliminating them entirely from the circuit at critical nodes. Propagation and arrival of an SET pulse to a latch is a strong function of circuit topology and input voltages. SET pulses must arrive at the latch input during setup-and-hold time to become an error. Pulses arriving at latch input outside setup-and-hold time requirements do not affect the circuit operation. For digital circuits, the ion hits are classified into two different categories: storage cell hits and combinational logic hits. Assuming uniform incident particle fluence, the number of hits on storage cells and combinational logic will be proportional to the area occupied by both types of logic. As the area of combinational logic circuits is almost always higher than that for storage cells (except in case of memory ICs), the number of errors due to a hit on combinational circuits is significantly higher for advanced technologies. If an ion hit is on a node within a storage cell, such as a latch or a memory cell, the data stored in the cell may flip if the deposited charge exceeds the critical charge. Design methods to mitigate latch hits usually introduce delays in the feedback loop of the latch to overpower transients. This technique has the drawback of increasing the write times for the latch. However, it is very effective and is currently being used by the design community. This paper does not deal with these types of hits. On the other hand, if the hits are within combinational logic circuits, the effect of the resulting transient pulse is a strong function of the hit node characteristics and the functionality of the hit node within the circuit [2], [3]. A pulse introduced by such an ion hit must propagate through the circuit and arrive at an output or arrive at a latch input. The path taken by the SET pulse is a strong function of the circuit topology and input voltages, as shown in Fig. 1. The arrival time of the SET pulse at the latch input is critical to overwrite actual data within that latch to cause an error as shown in Fig. 2. Modeling and characterization of these types of circuits have been extensively studied [1]–[5]. This paper presents a novel method that eliminates most combinational logic SET pulses using simple design techniques. This method requires additional gates and circuits to accomplish this goal, but the overall effects on area, speed, and power for an IC are negligible. Temporal methods for removing SET pulses use data latching at different times during a clock cycle. The voting circuit then removes the erroneous data and latches correct data in Latch 4.