I. Introduction
The Rapidly growing demand for larger bandwidth motivates RF circuits to move toward higher frequencies. At frequencies above 20GHz, GaAs-based HEMT and HBT processes occupied most of the applications in the past. Recent works have shown that the rapid development of CMOS devices have potential for building RF circuits at frequencies above 20GHz. Although LNAs using SOI CMOS process demonstrated excellent performances [1], the standard bulk CMOS process is still attractive due to cost consideration. There were some reports of bulk CMOS LNAs designed for frequencies above 20GHz. Common-gate configuration with resistive feed-through input stage is used in [2], implemented in a 0.18-m CMOS technology and achieves 15-dB gain and 6-dB NF at 21.8 GHz. The common-source input stage is utilized in [3], [4]. 12.86-dB gain and 5.6-dB NF are obtained of another 0.18-m CMOS LNA at 23.5 GHz [3]. A 20-GHz LNA fabricated in a standard 90-nm CMOS technology obtains a 6-dB gain and a 6.4-dB NF [4]. It is observed that standard bulk CMOS LNAs achieved comparable gain performance of GaAs-based pHEMT LNAs [5], but with much higher noise figure. Performance Comparison With Lnas for Frequencies Above 20GHz
Ref. | This work | [2] | [3] | [4] | [5] | |
---|---|---|---|---|---|---|
Process | 0.18-μm CMOS | 0.18-μm CMOS | 0.18-μm CMOS | 90-nm CMOS | 0.15-jum InGaP/ InGaAs pHEMT | |
Peak gain frequency (GHz) | 24 | 21.8 | 23.7 | 20 | 26.5 | |
Noise figure (dB) | 3.9 | 6 | 5.6 | 6.4 | 1.7 | |
Gain (dB) | 13.1 | 15 | 12.86 | 6 | 14.5 | |
chip size (mm2) | w/i pad | 0.34 | −- | 0.735 | 0.56 | 0.9 |
w/o pad | 0.16 | 0.05 | −- | −- | −- | |
I/O Return losses (dB) | 15/ 20 | −- | 11/22 | 20/20 | 10/10 | |
(mW) | 14 | 24 | 54 | 10 | 37.5 | |
Power Supply | 1 V | 1.5 V | 1.8 V | 1.5 V | 2.5 V | |
Circuit Topology | 2-stages, CS+CS | 3-stages, CGRF +CS+CS | 3-stages, CS+CS +CS | 1-stage, CS | 2-stages, CS+CS |
*CS: common source, CGRF: common gate resistive feedthrough