A new stress chip design for electronic packaging applications

Stress sensing chips are invaluable for structural analysis of electronic packages, and can be used for in-situ real-time measurement of thermally induced die surface stress. Four-point-bending calibration, wafer-level calibration and hydrostatic calibration have been used to calibrate the stress sensing chip. These methods are used to calibrate different piezoresistive coefficients B/sub 1/, B/sub 2/ or their combinations (B/sub 1/-B/sub 2/), (B/sub 1/+B/sub 2/) and (B/sub 1/+B/sub 2/+B/sub 3/). Hydrostatic calibration is a bottleneck to quick calibration. Only one chip can be calibrated at a time and it must be wire bonded. Also, the value of coefficients (B/sub 1/+B/sub 2/+B/sub 3/) obtained is not temperature compensated and precise temperature measurement is required. Thus, a quick and accurate calibration method is key to making stress sensing chips more acceptable for electronic packaging use. In this paper, a new (111) stress sensing chip design is presented, and an innovative calibration scheme is proposed. Calibration can be done at wafer level, giving large savings in calibration time over the die form process. The mechanism is based on thermal expansion of the Al micro-beams which produce out-of-plane shear stresses on the sensing elements under temperature change. The relationship of normalized resistance change against temperature was found experimentally. Stresses produced by the Al micro-beam are high enough for calibration, with 4.6/spl sim/5.4% difference of normalized resistance changes between resistors with and without micro-beam. Also, a simple 1D model was proposed to estimate the order of magnitude of the stress under temperature change.