I. Introduction
With the shrinking device scale and higher performance requirement of integrated circuits, the utilization of the advanced photolithography and anisotropic etching techniques are essential. The increasing number of interconnection layers requires highly planarized surface on every layer to ensure that the accumulated roughness of the layers are less than the depth of focus (DOF) of the lithographic stepper. An evenly polished surface satisfies two requirements, namely to ensure the good metal step coverage and to provide a field within the lithography depth of focus, that contact vias and metal wires can be well patterned [1]. The accumulated variation in film thickness will impair the process. Chemical–mechanical polishing (CMP) has become a key process for the Cu interconnects, low- materials and dual damascene process. Thermal Monitoring for CMP
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