Modelling charge-pump delay locked loops

This paper presents a new sampled-time model for charge-pump delay locked loops (DLLs). This novel model is used for jitter analysis, extending previous results and providing better insight to jitter transfer mechanisms in DLLs. The model includes both the effects of total line delay and the control loop of the DLL, and is applied to input jitter and internally generated jitter. This model is further extended to handle jitter effects related with the control charge-pump. Conclusions based on this model are finally presented, and confronted with previous knowledge and practical implementations in DLLs.