A 2.4 Gbps transmitter with programmable de-emphasis scheme for DDR3 memory interface

A 2.4 Gbps output driver for DDR3 memory interface with programmable de-emphasis scheme is proposed. There are 15 de-emphasis levels that can be programmed to eliminate inter-symbol interference (ISI) problem at high operating speed. The proposed output driver is implemented using low-voltage 45 nm CMOS process. Due to the DDR3 memory operating voltage is 1.5 V, transistor stacking technique is applied in the output driver design to avoid transistor gateoxide reliability issues. The driver's transmit impedance can be programmed between 20 Ω to 40 Ω and receive impedance of 100 Ω. The output slew rate is controlled at 4-6 V/ns. There are two compensation blocks to calibrate the output impedance and output slew rate across process, voltage, and temperature (PVT) variations.