Tuning the Germanium TFET: Device Optimization for Maximum Ion

As MOSFET scaling has attained the 22 nm node, alternative concepts are intensively being investigated. The concept of the Tunneling Field Effect Transistor (TFET) is currently being explored as one of the device concepts most likely to enable energy efficient computation that, in addition, can potentially outperform the conventional MOSFET. Attaining the necessary Ion (International Technology Roadmap for Semiconductors) (ITRS) 2011, 1,367 μA/μm, High-performance (HP) table Process Integration, Devices, and Structures (PIDS) 545 μA/μm, Low Operating Power Performance (LOP) table PIDS and 374 μA/μm Low Standby Power (LSTP) table PIDS is at present one of the major obstacles on the road towards establishing the TFET as a serious alternative to the MOSFET.