An effective BIST architecture for sequential fault testing in array multipliers

Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper we present, for the first time, a BIST architecture which does not require any DFT modifications in the multiplier structure and provides a fault coverage larger than 99% for a comprehensive sequential fault model (RS-CFM) for any multiplier size. Both robust and non-robust testing are considered. The applicability of the BIST architecture is further justified considering the case of the transistor stuck-open fault model, where a fault coverage larger than 99% is also achieved in any case.