An FPGA implementation of shift converter block technique on FIFO for UART

To meet the standard modern system wireless communication demands, the paper represents the implementation of bidirectional shift converter technique with FIFO circuit block and UART (Universal Asynchronous Receiver Transmitter) circuit block through FPGA device using Verilog HDL language to be applied in embedded system converter RS232 to USB (Universal Serial Bus). Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality.