Specific power illustration of proposed 7T SRAM with 6T SRAM using 45 nm technology

This paper is based on the observation of a various CMOS seven transistor SRAM cell for very high density and low power applications. This cell retains its data with leakage current and positive feedback without refresh cycle. These various 7T SRAM cell uses one word-line and one bit-line and NMOS transistor to control. Simulation and analytical results show purposed cell has correct operation during read/write and also the delay of new cell is 70.15% smaller than a six-transistor SRAM cell. The various new 7T SRAM cell contains 72.10% less leakage current with respect to the 6T SRAM memory cell using cadence 45 nm technology and power consumption during read and write operation are approximate 20.34% less than the conventional 6T SRAM memory cell.