Clock gating — A power optimizing technique for VLSI circuits

Clock gating is one of the power-saving techniques used on the Pentium 4 processor and in next generation processors. To save power, clock gating refers to activating the clocks in a logic block only when there is work to be done. From the earliest days of the Pentium 4 processor design, power consumption was a concern. The clock gating concept isn't a new one; however, the Pentium 4 processor used this technology to a large extent. Every unit on the chip has a power reduction plan, and almost every Functional Unit Block (FUB) contains clock gating logic. The work in this paper investigates the various clock gating techniques that can be used to optimise power in VLSI circuits at RTL level and various issues involved while applying this power optimization techniques at RTL level.

I. Introduction

With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. Though power should be optimized at all stages of the design flow, optimizations in early design stages have the greatest impact in reducing power [9], [10].