Automation of 3D-DfT Insertion

Using Through-Silicon Vias (TSVs) in three-dimensional stacked ICs (3D-SICs) has benefits in terms of interconnect density, performance, and power dissipation. For 3D-SICs, an extension of the Design-for-Test architecture based on die-level wrappers is required to enable pre-bond die testing as well as modular post-bond die and interconnect testing. This paper presents an approach that automates the insertion of die wrappers. Experimental results show that the user can perform automated 3D-DfT insertion through existing EDA tools with negligible area costs, and verify the proposed DfT by test pattern generation and simulation.

1 Introduction

Three-dimensional IC stacking by means of Through-Silicon Vias (TSVs) is a relatively new technology which has a number of advantages over conventional stacking methodologies [1]. TSVs are vertical copper or tungsten conducting nails passing through a thinned die. Typical TSV dimensions are diameter and height. The actual connection to the next die can be a direct copper-to-copper bond of the TSV onto a small landing pad, but today is often implemented by means of a CuSn micro-bump, of which typical dimensions are diameter at pitch. As they form direct vertical interconnects between stacked dies, TSVs allow a much larger number and higher density of interconnects than conventional wire-bonds. Due to their geometry TSVs have relatively low capacitance and inductance, and thus provide high bandwidth operations and low power consumption [2].