High-frequency through-silicon Via (TSV) failure analysis

Despite the many advantages of 3D ICs, the yield loss experienced during the 3D IC fabrication process limits the commercialization of 3D IC products. In this study, we propose a novel method for TSV failure analysis and analyze TSV failures electrically to detect failures and their locations in TSV-based 3D IC.

I. Introduction

Recently, much research and development of through-silicon via (TSV)-based 3-dimensional integrated circuits (3D ICs) has been done to realize a higher package density, smaller form factor, higher system bandwidth and lower power consumption by virtue of stacking dies with TSVs. Because the TSV is a vertical link hat provides a short interconnect length between the stacked dies, TSV-based 3D integration technologies are highly advantageous due to their reduced parasitic resistance and inductance of the TSV-based channel compared to lateral chip placement and a wiring integration approach. In addition, the number of input/outputs (I/Os) in 3D ICs, which is directly affected by the number of TSVs, must be increased by several thousands of orders to realize system bandwidths featuring hundreds of GB/s, especially for high-end graphic applications.