I. Introduction
In recent years, the development of large-scale networks with spiking neurons [1] and adaptive synapses based on spike-timing dependent plasticity (STDP) [2] has suggested new avenues of exploration for brain-like cognitive computing. A massively scaled example of this work is described in [3], which reports a cortical simulation at the scale of a cat cortex (109 neurons and 1013 synapses) using supercomputers. When compared to a brain that consumes 20W and occupies just 2L, the memory, computation, communication, power, and space resources needed for such a software simulation are tremendous. Consequently, there is an enormous opportunity for efficient, dedicated VLSI hardware that moves beyond prevalent von Neumann architectures to ultimately enable true large mammalian brain-scale networks (1010 neurons and 1014 synapses) with extremely low power consumption (<1kW) and volume (<2L) for ubiquitous deployment. Achieving this ambitious goal will demand a combination of advances in architectures designed to exploit spiking network properties coupled with exploitation of continued CMOS scaling.