Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives

This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 mum are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-mum CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved