I. Introduction
Advances in integrated circuit processing and packaging technology are enabling the fabrication of transistors and interconnections for circuits in the gigahertz range. For example, radio frequency (RF) circuits made in 90-nm CMOS technology with SiGe bipolar transistors are comparable in performance to those made with the more expensive III–V semiconductors. With advanced fine-line and microvia packaging technologies, many critical passive components can be made in a small area of the package substrate. Moving passive circuit elements from the die to the package reduces the die size and cost, and improves critical performance metrics such as the phase noise of voltage-controlled oscillators (VCOs). The phase noise of a VCO is inversely proportional to the square of the factor. With the best-known practice, a factor of 10–20 is achieved for on-die inductors, whereas a factor larger than 20 can be achieved on the package. To improve the mechanical reliability of the IC-to-package interface, a liquid epoxy is filled into the gaps between the die solder bumps. Ideally, this epoxy uniformly fills the space without air bubbles or voids and hardens after curing. To maximize the factor and inductance value of the on-die inductors, some solder bumps directly under the inductor should be removed. This selective and nonuniform removal of the solder bumps makes the flow of the liquid epoxy irregular and weakens the die to package interface. With package inductors, this problem is eliminated.