A high-speed serial data acquisition scheme based on Nios II

This paper proposes a high speed serial data acquisition scheme. The scheme adopts Nios II soft processor in FPGA instead of application of specific chips in digital system to realize and control serial data acquisition, and especially focuses on the hardware designment with Quartus II and software development with Nios II EDS. This design shortens the design processs, simplifies the circuits, and increases data reliability. Simulation and testing results show that the data receiving is accurate, which verifies the validity of the design.