A comprehensive soft error analysis methodology for SoCs/ASICs memory instances

Memory blocks are important features of any design, in terms of functionality, silicon area and reliability. Embedded SRAM instances are critical contributors to the overall Soft Error Rate of the system, requiring a careful consideration of the reliability aspects and adequate sizing of the error mitigation capabilities. While error detecting and correcting codes are widely available and particularly effective against most types of Single Event Effects, Multiple Bit Upsets and progressive errors accumulation may defeat the error correction capabilities of standard SECDED codes. Accordingly, the paper presents an overall approach to the structural and functional SER analysis of the memory instances in addition to error mitigation efficiency estimation. Moreover, intrinsic, nominal, SER figures are not a realistic indicator of the memory behavior for a given application. We propose instead, an opportunity window metric, associated to the notion of data lifetime in the memory, as extracted from functional simulations. Lastly, based on the opportunity window figures, targeted and efficient fault simulation campaigns can be prepared to estimate high-level functional failures induced by Single Events. The overall memory SER evaluation aims at assisting the designers to improve the performances of the design and to document the reliability figures of the system.