An efficient voltage-mode class-D power amplifier for digital transmitters with delta-sigma modulation

A high efficiency voltage-mode class-D power amplifier for digital transmitters with delta-sigma modulation is demonstrated using a 0.13-μm 1.2-V silicon-on-insulator (SOI) CMOS technology. To minimize the overlap of ON time of both the PMOS and the NMOS transistors, a shoot-through current reduction technique was employed. Distortion induced by parasitic inductance was mitigated with integrated on-chip capacitors. The amplifier was tested with periodic signals, envelope delta-sigma modulation (EDSM) signals, and band-pass delta-sigma modulation (BPDSM) signals at 800MHz. Peak drain efficiencies of 75, 62, and 55% were obtained for these inputs, together with ACPR of -60dBc for EDSM EDGE signals and -43dBc for BPDSM CDMA signals.