Design procedure for settling time minimization in three-stage RNMC amplifiers

This paper presents a new method in time domain for optimizing the settling time in three stage amplifiers with reversed nested Miller compensation (RNMC). This procedure allows the compensation capacitors to be sized to achieve the best settling behavior of the closed-loop op-amp. To show the effectiveness of the method, a typical amplifier in 1V, 90 nm CMOS technology is designed. Simulation results show that using this method, settling time of three-stage RNMC amplifiers significantly improved compared to conventional design method. Also, the figure of merit of this amplifier shows the ratio settling-time/power-consumption of amplifier is greater than the other NMC amplifiers.