High-Performance FPGA Implementation of Discrete Wavelet Transform for Image Processing

In this paper, two high-performance FPGA implementations of discrete wavelet transform (DWT) and relevant inverse discrete wavelet transform (IDWT) are proposed. At first, a DWT/IDWT aiming at a special wavelet (Daubechies 8 wavelet) is implemented. The maximum clock frequency of this design can respectively achieve 200MHz on an Altera Cyclone II platform - DE II development board, which is an obvious advantage, comparing with similar literatures. Besides that, a universal discrete wavelet transform is designed, in which the wavelet type and the order of DWT/IDWT can be changed. It is flexible and configurable for different applications. The maximum clock frequency of this universal discrete wavelet transform design can achieve 100MHz on the DE II development board. For optimization, distributed arithmetic, look-up table architecture and pipeline technology are employed in our design. Finally, through an image test, our design is verified efficient in hardware image processing based on wavelet transform theory.

I INTRODUCTION

Nowadays, implementing digital signal processing algorithms on field programmable gate arrays (FPGAs) becomes a growing trend, for the reason that FPGAs have merit on merging digital signal processing algorithms with other control logic. Discrete wavelet transform (DWT) is a classical signal transform algorithm, which is increasingly applied on many areas, such as signal instantaneous analysis, image edge detection, image denoising, pattern recognition, data compression and so on.