Low-complexity integrated circuit aging monitor

Integrated circuit aging effects are more and more pronounced with the continuous technological downscaling. These effects degrade circuit operation which is mainly observed as increased input-to-output delay of circuit components. Eventually, the circuit falls out of its specifications. Countermeasures are needed to prevent or reduce such degradation. Aging monitoring can be very beneficial since it can predict circuit failure and/or activate mechanisms to avoid failure. Most of the present aging monitors are based on reporting abnormal input-to-output signal delays on the critical path of the circuit. However, present approaches introduce additional circuit complexity, use complicated analog design, use non-standard cells etc. We propose a low-complexity aging monitor based on standard library cells, offering simplicity and flexibility of its design, integration and use. The designer could instantiate many monitors throughout the integrated circuit. The user can simply read the “aging code” placed in a register in each monitor and determine the “age” of the circuit, predict a circuit failure and/or take an appropriate action. This is especially useful in microprocessors which are designed with dependability in mind.