Scaled LTPS TFTs for low-cost low-power applications

Low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) have emerged as a promising technology for applications such as low-cost sensor networks. In this paper, we propose a LTPS TFT device optimization methodology based on scaling of silicon body (T
_si
) and buried oxide thickness (T
_box
). The proposed approach is applicable for both digital and analog circuits. Results show that using the proposed device we can achieve 133X improvement in oscillation frequency of a three-stage ring oscillator (RO) and 31% improvement in operational amplifier (OPAMP) gain (T
_si
=10nm and T
_box
=10nm) compared to the traditional device structures. We believe that proper optimization of TFT device geometry parameters is necessary to realize low-power, high-performance, and low-cost LTPTS TFT digital & analog/RF circuits.