Circuit-level delay modeling considering both TDDB and NBTI

With aggressive scaling down of the technology node, the time-dependent dielectric breakdown (TDDB) and negative biased temperature instability (NBTI) are becoming key challenges for circuit designers. Both TDDB and NBTI significantly degrade the electrical characteristic of the CMOS devices. A delay model considering TDDB and NBTI is proposed in this paper. The output degradation of the breakdown gate is considered in circuit-level delay analysis. Traditionally, it is considered the TDDB degradation always degrades the circuit delay. However, this paper shows the TDDB effect may boost up the circuit speed. The spatial correlation of TDDB effect is also demonstrated in this paper and shows the difference of 40% in circuit delay depending on the location of the breakdown gate in the signal path.

I. Introduction

With technology scaling down, the aging effect and longterm reliability of the gate dielectrics are becoming key challenges for circuit designers [1]. During the working life of devices, many physical phenomena will degrade the electrical parameters such as drain current and threshold voltage. In this paper, TDDB and NBTI are addressed because of their severity in nano-scale devices.