PET system synchronization and timing resolution using high-speed data links

Current PET systems with fully digital trigger rely on early digitization of detector signals and the use of digital processors, usually FPGAs, for recognition of valid gamma events on single detectors. Timestamps are assigned and later used for coincidence analysis. Good timing resolution is important, allowing better rejection of singles and leading to increased reconstructed image quality. In order to maintain a decent timing resolution for events detected on different acquisition boards, it is necessary that local timestamps on different FPGAs be synchronized. Sub-nanosecond accuracy is mandatory if we want this effect to be negligible on overall timing resolution. This is usually achieved by connecting all boards to a common backplane with a precise clock delivery network; however, this forces a rigid structure on the whole PET system, and clock synchronization gets more difficult as the size of the system grows. Instead, we propose a backplane-less PET system in which DAQ boards are connected by single full-duplex high-speed data links. Data encoding with embedded clock is used to avoid frequency differences between local oscillators. Timestamp synchronization between FPGAs with clock period resolution is maintained by means of data transfers in a way similar to the IEEE1588 standard. Finer resolution is achieved by reflection of received clocks and phase difference measurement on the transmitter. A hierarchic clock distribution ensures that accumulation of time uncertainty is minimized. It is crucial that data transceivers have very low latency uncertainty in order to achieve the desired timestamp accuracy; we discuss the availability of off-the-shelf hardware for these implementations.