1. INTRODUCTION
During the last years, continuous-time (CT) sigma-delta analogue-to-digital converters (ADCs) have become very popular as they offer inherent anti-aliasing filtering and low power dissipation. However, CT implementations suffer from several non-idealities such as process variations, excess loop delay (ELD), jitter sensitivity and non-linearity of the feedback digital-to-analogue converter (DAC) in the multibit case. The CT filter in the modulator is highly susceptible to process variations as its coefficients depend on the absolute value of resistors and capacitors. While the matching between capacitors or resistors is in the order of or less, the product of their absolute values can vary up to . This leads to a deviation from the desired noise-transfer-function (NTF) and, potentially, to an increment of the in-band-noise (IBN) and instability. Consequently, correction techniques, such as [1], [2], [3], [4], are generally required so as to counteract such deviation.