Contents I. Introduction
In modern high-speed communication systems, single channel data-rate is being pushed to 17 Gbps and the roadmap is towards 25 Gbps and beyond for next generation products [1]. In order to make a high-speed channel working in such a high data-rate, special cares must be taken into account in physical aspects in the channel design including dielectric properties of PCB substrate materials, surface roughness of conducting metals, discontinuities due to the routing bends and signal transitions through vias in the ASIC BGA (Ball Grid Array) areas and DC blocking structures. Since dielectric loss is proportional to the frequency while the conductor loss is proportional to the square root of the frequency, the dielectric loss dominates the total loss, especially in the frequency range above 1-2 GHz [2]. In real system designs, the channel length for a specific SerDes link is usually fixed with the tolerance of a couple of inches, which roughly determines the total loss of the channel. For a given long SerDes channel, two methods can be used to insure the channel performance above a certain level. The first solution is to use low loss PCB substrate materials. The state of arts of the PCB industry indicates that the DF (dissipation factor) value for low loss PCB substrates can be manufactured in the level around 0.006 in real products, which is almost one-third of the DF value of a regular FR4 substrate. The second solution is to use EDC (Electronic Dispersion Compensation) equalizers to compensate the signal degradation due to the channel loss and the dielectric dispersion. The advantage of using the low loss PCB substrate materials is no impacts on a board surface mounting density and an inner layer routing density, but with the punishment of higher PCB cost. For the solution about adding EDC equalizers, the board surface mounting density and the inner layer routing density are decreased. In addition, extra chip cost is another drawback of the solution. However, the total usable channel length is able to be extended longer depending on the driving strength of the EDC chips. Or in other words, the channel has more margins to meet a given BER (Bit Error Rate) requirement. As for surface roughness, which is related to both the dielectric loss and the conductor loss [3], what a signal integrity engineer can do is to choose the PCB with relative smooth copper surfaces. In reality, since the copper surface is intentionally to be made coarse to meet the peeling strength requirement for PCBs, no too many selections are available until new technology comes up to solve the peeling strength for smooth surfaces. Though via transitions in the ASIC BGA areas can be optimized for better channel performance [4]–[6], it is the topic beyond the interest of this paper. This paper will focus on the impacts of DC blocking via structures on the performance of SerDes channels.
