Ultra-low series resistance W/ErSi2/n+-Si and W/Pd2Si/p+-Si S/D electrodes for advanced CMOS platform

A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (R
_c
) of 8.0×10
^-10
Ω·cm
²
and the electrode's sheet resistance (R
_sheet
) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi
₂
and W/Pd
₂
Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was fabricated and the ring oscillator speed performance was evaluated.