Self checking FIFO queue

The advances in VLSI technology have made many changes not only in the architecture of computer and digital systems, but also in the amount of hardware that can be implemented in a single chip which makes it possible to include the entire system in single chip. But as the scale of integration has increased so also has the occurrence of intermittent faults. The detection of intermittent faults requires the use of concurrent error detection CED (coding) techniques. This paper investigates the use of Berger code as a mean of incorporating CED into a self checking FIFO queue.