FPGA Implementation of CORDIC-Based Square Root Operation for Parameter Extraction of Digital Pre-Distortion for Power Amplifiers

Square root operation is a critical operation in the parameter extraction algorithm of the digital pre-distortion for power amplifiers. Accuracy and speed of square root operation are important factors in the digital pre-distortion parameter extraction process. But square root operation is difficult to realize with normal method for achieving high throughput. In this paper, a CORDIC algorithm, which is realized with pipeline structure on FPGA, is introduced to realize the square root operation. The calculation precision can be improved by increasing the iteration numbers, optimizing and selecting the parameters related to iterations. The CORDIC algorithm is implemented in FPGA and can be called through the Nios II Custom Instruction in Altera Stratix II development platform. The validation results demonstrate that the proposed method simplifies the digital pre-distortion parameter extraction algorithm and speeds up the computation.