Fast IO buffer modeling using neural network methods

This paper provides an overview of a fast modeling approach for modeling the nonlinear IO buffers for signal integrity based simulation and design of high-speed electronic interconnect and packages. Techniques based on artificial neural network (ANN) modeling are developed, where the neural network is trained to learn from IO buffer data, and trained neural network becomes fast models representing the buffer during signal integrity simulation and design. The ANN approach is more accurate than typical empirical models, and is faster than detailed models such as detailed transistor-level or physics-based models.