How to do RF-BiST with virtually no extra circuits for RF-SoC products?

This paper describes novel RF Built-in Self Test (RFBiST) and RF Built-in-Self-Calibration (RF-BiSC) techniques that can test the performance of RF SoC's using on-chip resources as both test stimuli and response analyzers. Our RFBiST approach is to fully utilize existing on-chip circuitry to prevent adding extra die area, while remaining capable of performing various RF-SoC self-tests. Successful RF-BiST examples include internally measuring RF oscillators with onchip digital signals from an All-Digital Phase Locked Loop (ADPLL). Other RF-BiST examples cover various contributors to Error Vector Magnitude (EVM) such as gain, linearity, and phase noise. Functional RF-BiSTs, such as loop-back methods, can be verified from GSM/EDGE to WLAN SoCs through good correlation with comparable external tests. Additionally, RFBiST/ BiSC with on-chip digital controllers and compensation networks can help drastically reduce the cost of phase and amplitude calibration and the deployment time with improved uniformity for phased-array RADARs, benefiting both future military and commercial RADAR systems considerably.

I Introduction

Recent advances in silicon-based CMOS and BiCMOS technologies have enabled multiple radios to be integrated onto the same die alongside complex digital circuitry such as the Central Processor Unit (CPU) and digital signal processing (DSP) engines, as well as a large amount of memory on-chip. Wireless LAN (WLAN), Bluetooth, GPS, and FM radios can all now be integrated on a single chip, making highly-integrated RF-SoC (System-On-a-Chip) products a reality. This high level of integration has put a huge burden on testing technology to keep up with the demands ofhigher clock speeds and the ever increasing data rates realized by the wide-bandwidth digital modulation techniques such as 64 Quadrature Amplitude Modulation (64QAM) with Orthogonal Frequency Division Multiplexing (OFDM). Traditionally, RF devices have been tested in a full functional mode by sending thousands of packets of data to be demodulated and converted into system performance parameters such as Error Vector Magnitude (EVM) or Bit Error Rate (BER) results. These methods complicate the production test environment with expensive and complex equipment that is required to perform the signal generation/demodulation and analysis of the signal of interest. This presents a bottleneck in production capacity and increases overall test cost as traditional methods are not easily run in parallel, as each device under test (DUT) must have access to external equipment in a production environment.