An Etch-Stop Barrier Structure for GaN High-Electron-Mobility Transistors

We present an etch-stop barrier structure for GaN high-electron-mobility transistors. With this new etch-stop structure, gate recess can be precisely controlled while maintaining a low surface defect density. Normally off GaN metal-insulator-semiconductor FETs fabricated using the new technology demonstrated a record effective channel mobility of 1131 cm²·V^-1·s^-1 with a subthreshold slope of 62 mV/decade. Due to the low interface density of states, these devices have very low hysteresis and negligible frequency dispersion in the capacitance-voltage (C-V) measurements.

I. Introduction

Gate recess is a very important process technology for AlGaN/GaN high-electron-mobility transistors (HEMTs). In RF AlGaN/GaN HEMTs, gate recess has been used to reduce short-channel effects and improve the current gain cutoff frequency [1]. In power switching applications, gate recess has been widely used to fabricate normally off AlGaN/GaN HEMTs [2]–[5]. Since both GaN and AlGaN are very inert to wet chemical etchants, chlorine-based dry etching is typically used for gate recess. There are, however, two major drawbacks in dry plasma etching:1) it causes plasma damage creating high density of defect states and degrading the channel mobility in the recessed region [4]; and 2) due to the changes in plasma etch rate, it is difficult to control the recess depth precisely by a timed etching, which causes a variation in transconductance and threshold voltage . This problem becomes even more challenging when multiple devices with different gate lengths are recessed together, as the etching rates are different for different aspect ratios.