Density-of-State and Trap Modeling of Low-Voltage Electric-Double-Layer TFTs

The modeling of low-voltage oxide-based electric-double-layer (EDL) thin-film transistors (TFTs) is reported. A simple model with a constant mobility (i.e., 30 cm
²
/V · s), interface trap density (i.e., 10
¹⁰
cm
^-2
), and two-step subgap density of states (DOS) is proposed. This model can describe the electrical characteristics of EDL TFTs well. Oxide-based EDL TFTs show much lower DOS than the typical oxide TFTs. Our results can give hints to optimize the process and electrical performance of EDL TFTs. If both DOS and interface traps are optimized, the on/off-current ratio could be improved.