Extraction Technique of Trap Densities in Thin Films and at Insulator Interfaces of Thin-Film Transistors

We have developed an extraction technique of trap densities in thin films and at insulator interfaces of thin-film transistors (TFTs). These trap densities can be extracted and separated from capacitance-voltage and current-voltage characteristics by numerically calculating , Poisson equation, carrier density equations, and Gauss' law. The outstanding advantages are intuitive understandability and a simple algorithm. The validity is confirmed using device simulation, and actual trap densities are extracted for a high-temperature poly-Si TFT.

I. Introduction

Thin-Film transistors (TFTs) are key devices for giant microelectronics because they can be fabricated on large substrates at low cost [1]. Therefore, they are applied to not only flat-panel displays such as liquid-crystal displays [2], organic light-emitting diode displays [3], and electronic papers [4] but also photosensing devices such as ambient light sensors [5], image scanners [6], and artificial retinas [7], as well as general electronics such as information processors [8].