Top-Gate Amorphous Silicon TFT With Self-Aligned Silicide Source/Drain and High Mobility

We report a process for top-gate amorphous silicon thin-film transistors (alpha-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280degC. The thermal budget is compatible with flexible polymer substrates. The fabricated devices exhibit threshold voltages of ~2.7 V, saturation electron field-effect mobility of 1.0 cm
²
/V ldr s, subthreshold slope of 600 mV/dec, and on/off ratio of ~2 times 10
⁶
. These top-gate alpha-Si TFTs with self-aligned silicide S/D have dc performance that is comparable to that of conventional bottom-gate alpha-Si TFTs. Our results suggest that the top-gate alpha-Si TFT geometry merits reevaluation for industrial use.