I. Introduction
Recently, silicon-on-insulator (SOI) structure has been in the phase of mass production, and the novel structures such as double gate and trigate have been extensively studied as a promising candidate for near future MOSFETs[1] [2]. The successive reduction of device size will require the channel region with nanometer scale thickness. For example, ultrathin body double-gate (UTBD) FET is reported, whose body thickness is less than 10 nm [3]. The most basic form of the channel region in the aforementioned structures is a semiconductor slab sandwiched by insulating layers. Few studies have been reported on the relation between the slab shape and the electronic structure using a first-principles calculations [4]. On the other hand, in the SOI and silicon germanium on insulator technology, the strain applied to the channel region is intentionally used to improve device performance [5]. Further, strain spontaneously occurs in the channel region during device manufacturing process for the complex structures such as the multigate. Therefore, it is an important and fundamental issue for near future semiconductor devices to study the electronic transport parameters of the strained semiconductor slabs with nanometer scale thickness.