Design of On-Chip Transformer With Various Coil Widths to Achieve Minimal Metal Resistance

A layout design algorithm of a variable-width transformer is proposed to minimize metal resistance in this letter. The proposed algorithm can rapidly design metal widths in each coil of a planar transformer for a given chip area. Two on-chip transformers with identical self-inductance are fabricated to verify the proposed algorithm in 90-nm CMOS technology. Measurement results demonstrate the improvement of metal resistance approximates to the value of 11.6%. Results of this study provide an effective algorithm to design a minimal-loss transformer for radio frequency integrated circuit applications.