Contents I. Introduction
Because of integration problems associated with the capacitor of the conventional dynamic-RAM (DRAM) cell in nanoscale CMOS technology, interest in “capacitorless” DRAM cells, in which data storage is effected by charging/discharging the floating body of a silicon-on-insulator (SOI) MOSFET, has recently grown [1]–[8]. Whereas the early focus of interest in the floating-body cell (FBC) was on the partially depleted (PD) SOI MOSFET [1], it has expanded now to include CMOS devices with more potential scalability, i.e., fully depleted (FD) SOI MOSFETs [2], [5], [7] and FD double-gate (DG) FinFETs [3], [4], [8]. The FBCs rely on the dependence of channel current , or threshold voltage , on the floating-body charge condition, or body–source voltage (, the quasi-Fermi potential separation) [5], [9]. For the FD (n-channel) cells, it is pervasively acknowledged [2]–[5], [7], [8] that a hole-accumulation layer must be induced by substrate or back-gate bias to form a “deep potential well” for hole storage, as thought to exist naturally in the PD cell [1], [6]. The published explanations of the capacitorless FBC operation based on the notion of a potential well, and the cell-design implications of it, are inadequate and misleading, as will be shown in this letter. Using numerical device simulations and analytical modeling, we physically overview the basic operation of the FBC, revealing new insights that could lead to optimal cell designs.
