Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p
⁺
-n junction. The device was made on a semi-insulating InP substrate with Si
⁺⁺
implant for the n-channel and Be/P co-implant for the p
⁺
-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10
¹⁶
/cm
³
.