Design of a PLL based frequency synthesizer for WiMAX applications

In this paper a PLL-based frequency synthesizer for WiMAX application is designed and simulated via MATLAB and ADS2008 using a 0.13um CMOS technology. Synthesizer with fractional-N structure is utilized to achieve high resolution, high switching speed, and high noise performance. To improve the linearity and the phase noise of the VCO, we employ a gain-linearizer block at the input of VCO. The simulation results show a phase margin higher than 50°, a phase noise lower than -120dBc/Hz @1MHz, and a settling time about 3μsec. In order to reduce the power dissipation, TSPC logic is used to design a programmable counter which needs less than 1mW in 2GHz.